The Securities and Exchange Commission (SEC) has mandated that all Broker/Dealers trading securities directly on an Exchanges or Alternative Trading Systems (ATS) are responsible to establish, document, and maintain a system of risk management controls and supervisory procedures that are reasonably designed to:

• Systematically limit the financial exposure that would arise as a result of market access to prevent orders that exceed appropriate pre-set credit or capital thresholds, or appear erroneous;
• Ensure compliance with all regulatory requirements that are applicable pre-entry on a per order basis and prevent restricted orders from trading, and restrict unauthorized access;
• Document and record the results, provide immediate post-trade execution reports to appropriate surveillance personnel, perform a documented review to demonstrate the effectiveness of the system at least annually, and certify annually.

The challenge is to create a system that inputs the proprietary information for each customer from the broker, inputs every trade from the “Naked access customer”, undertake the Financial Risk Management Control testing and verification, and sends the valid trades on to the exchange, with the lowest latency impact on each trade. Any delay in verification means a loss of a trading opportunity and directly impact the ability of the trading company to compete effectively.

Verification systems employing the server’s main processors suffer from unacceptable bottlenecks. Tests on file servers using “standard” 10 Gigabit Ethernet server network interface cards have shown that when performing TCP transfers through their native stacks, even 2.2 GHz processors can be close to 100% utilized while only achieving rates of less than 5 Gbits/s. Basically, the processor consumes significant numbers of processing cycles in the course of traversing through the protocol stack, assembling the data into properly formatted packets and calculating checksums. The processors become saturated while attempting to perform these cycles, even before they are able to reach the 10 Gbit/s rates. To solve this problem, engineers are resorting to specialized hardware to check for relevant data on the network card and then pass these to the main processor. This approach yields a significant improvement in response time.

In order to improve performance further and reduce delay introduced because of the verification step, it is possible to sidestep the main processor altogether and perform verification on the network processing card.

AdvancedIO’s network-side processing architecture using FPGAs allows complete monitoring and comparisons to be accomplished at hardware speeds without involving the host processor; trade information never leaves the network card keeping latency ultra low. Memory arrays on AdvancedIO products are built to accommodate multiple large programmable lookup tables and to execute in minimum time, ideal for this application. Our low latency hardware designs are specifically built to eliminate any latency and overhead found in typical network card designs, including physical interfaces, shortest path routing, and buffers. This is a significant competitive advantage in a business where having the lowest latency Financial Risk Management Control System is a must.

AdvancedIO provides best of class ultra low latency 10 Gigabit Ethernet FPGA cards enabled with an easy to use application development framework. Our team’s expertise is honed from years of providing solutions for the Defense, Telecom, and Financial markets. Customers rely on our expertise to deliver superior products on time and on budget.